-----------------------final-----------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:05:23 02/02/2011 
-- Design Name: 
-- Module Name:    topdma_rs_ram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 

--**********************
--Check for capital and small spelling of the signals
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.LCSE.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity topdma_rs_ram is
	port(
			Reset    : in  std_logic;           -- Asynchronous, active low
			Clk      : in  std_logic;           -- System clock, 20 MHz, rising_edge
			RS232_RX : in  std_logic;           -- RS232 RX line
			RS232_TX : out std_logic;           -- RS232 TX line
			-----------------------------------------------------------------------------------
			switches : out std_logic_vector(7 downto 0);  -- Switch status bargraph
			Temp_L   : out std_logic_vector(6 downto 0);  -- Less significant figure of T_STAT
			Temp_H   : out std_logic_vector(6 downto 0);  -- Most significant figure of T_STAT
		  -----main control--------------------------------------------------------------------
			DMA_ACK   : in  std_logic; --recognition and sharing of buses by the main processor
			Send_comm : in  std_logic; --start of data tx
			DMA_RQ    : out  std_logic; --request for bus to the processor
			READY     : out  std_logic ---=1 when processor is idle, 0-> processor is busy 
			);
	end topdma_rs_ram;

architecture behavior of topdma_rs_ram is

-------------------------------------------------------------------------
  -- Component for RS232top
---------------------------------------------------------------------------

	component RS232top is
		port(
			 Reset     : in  std_logic;   -- Low_level-active asynchronous reset
			 Clk       : in  std_logic;   -- System clock (20MHz), rising edge used
	 
			Data_in	  : in  std_logic_vector(7 downto 0);-- Data from dipswitches
			Valid_D   : in  std_logic;   -- Start_TX, TX button-- from spartan system, low when data is valid
			Ack_in    : out std_logic;   -- ACK for data received, low once data-- has been stored
			TX_RDY    : out std_logic;   -- System ready to transmit
			TD        : out std_logic;   -- from spartan system-- RS232 Transmission line
			RD        : in  std_logic;   -- from spartan system-- RS232 Reception line
			Data_out  : out std_logic_vector(7 downto 0);  --rx by spartan system--barleds, from tx rs232
			Data_read : in  std_logic;   -- 
			Full      : out std_logic;   -- Full internal memory
			Empty     : out std_logic);  -- Empty internal memory
		end component;

-------------------------------------------------------------------------
  -- Component for ram
---------------------------------------------------------------------------

	component RAM is
		port(
			
			Reset 	: in std_logic;
			Clk 		: in std_logic;								
			Databus 	: inout std_logic_vector( 7 downto 0); ---data bus
			Address 	: in std_logic_vector(7 downto 0);  --address bus
			CS 		: in std_logic;			--chip select
			write_en : in std_logic;   --write enable
			OE 		: in std_logic;			--read enable
			switches : out std_logic_vector(7 downto 0); ---switch state
			Temp_L 	: out std_logic_vector(6 downto 0);		---7 segment display lowest temperature value of thermostat
			Temp_H 	: out std_logic_vector(6 downto 0));		---7 segment display highest temperature value of thermostat
		
		end component;


-------------------------------------------------------------------------
  -- Component for dma
---------------------------------------------------------------------------

	component DMA is
		port(
			
			Reset     : in  std_logic;--asynchronous reset
			Clk       : in  std_logic;--20 MHZ
   
	----------------recieve data from rs232 to dma--------------------------------
			RCVD_Data : in  std_logic_vector(7 downto 0);--
										---RX_Full=0 then the fifo is not full it can rx data from the dma
										---RX_Full=1 then the fifo is full and cant recieve more data
			RX_Full   : in  std_logic;--status signal RX internal memory full--from rs232 to dma
									--RX_Empty=0 fifo is full.then rs232 tx data to dma
									--RX_Empty=1 fifo is empty.then rs232 waits to tx data to dma
			RX_Empty  : in  std_logic;--status signal RX internal memory ---------from rs232 to dma
			Data_Read : out  std_logic;--request to read data from the rs232
   
	--------------------transmit data from dma to rs 232------------------------------
			TX_RDY    : in  std_logic;--state of machine serial tx
			ACK_out   : in  std_logic;--ack for data rx from rs 232..data from rs232 to pc
			Valid_D   : out  std_logic;--valid data sent to rs232TX
			TX_Data   : out  std_logic_vector(7 downto 0);--send data to serial line
   
   -------------RAM------------------------------------------------------
			CS        : out  std_logic;--chip select
			Write_en  : out  std_logic;---write data to ram 
			OE        : out  std_logic;--read  from ram
			Address   : out  std_logic_vector(7 downto 0); --address bus
			Databus   : inout  std_logic_vector(7 downto 0); --system data bus
	
	-----main control-----------------------------------------
			DMA_ACK   : in  std_logic; --recognition and sharing of buses by the main processor
			Send_comm : in  std_logic; --start of data tx
			DMA_RQ    : out  std_logic; --request for bus to the processor
			READY     : out  std_logic);  ---=1 when processor is idle, 0-> processor is busy 
		end component;

------------------------------------------------------------------------
  -- Internal Signals
------------------------------------------------------------------------

-----------------dma------------------------------------------
signal RCVD_Data: std_logic_vector(7 downto 0);--connects Data_out(rs232) n RCVD_Data(dma)
signal RX_Full:  	std_logic;
signal RX_Empty:  std_logic;
signal TX_RDY:  	std_logic;--signal to connect rs232 n dma of same name
signal Ack_out:  	std_logic;--siganl to connect Ack_in (rs232) n ACK_out(dma)
--signal DMA_ACK:  	std_logic;
--signal Send_comm  std_logic;
----------ram-----------------------------------------------------
signal Databus:  	std_logic_vector(7 downto 0);
signal Address:  	std_logic_vector(7 downto 0);
signal CS:  		std_logic;
signal OE:  		std_logic;
signal Write_en:  std_logic;
--------------rs232-----------------------------------
--signal RD:   std_logic;
signal Valid_D:  std_logic;
--signal Data_in:  std_logic_vector(7 downto 0);
signal Data_read:  std_logic;--connects Data_read(rs232) to Data_Read(dma)
signal TX_Data : std_logic_vector(7 downto 0);
---------------------------------------------------------------------------

begin

rs:RS232top
	port map(
			Reset		=>	Reset, -- Low_level-active asynchronous reset
			Clk		=>	Clk,   -- System clock (20MHz), rising edge used
	 
			Data_in	=>	TX_Data,-- Data from dipswitches
			Valid_D	=>	Valid_D, -- Start_TX, TX button-- from spartan system, low when data is valid
			Ack_in	=>	Ack_out, -- ACK for data received, low once data-- has been stored
			TX_RDY	=>	TX_RDY,-- System ready to transmit
			TD			=>	RS232_TX,   -- from spartan system-- RS232 Transmission line
			RD			=>	RS232_RX,  -- from spartan system-- RS232 Reception line
			Data_out	=>	RCVD_Data,  --rx by spartan system--barleds, from tx rs232
			Data_read=>	Data_read,    -- 
			Full		=>	RX_Full,     -- Full internal memory
			Empty		=>	RX_Empty);  -- Empty internal memory
	

--------------------------------------------------------------
full_ram: RAM
	port map(
			Reset		=>	Reset, 
			Clk 		=>	Clk,								
			Databus		=>	Databus,  ---data bus
			Address 	=>	Address,  --address bus
			CS 			=>	CS,			--chip select
			Write_en	=>	Write_en,    --write enable
			OE 			=>	OE,		--read enable
			switches	=>	switches,  ---switch state
			Temp_L 		=>	Temp_L, ---7 segment display lowest temperature value of thermostat
			Temp_H 		=> Temp_H);	
-------------------------------------------------------------------------
dma_controller:DMA
	port map(
			Reset		=>	Reset,           
			Clk   		=>	Clk,
			RCVD_Data	=>	RCVD_Data, --signal --to connect Data_out(rs232)
			RX_Full   	=>	RX_Full,
			RX_Empty  	=>	RX_Empty,
			Data_Read 	=>	Data_read,
			TX_RDY    	=>	TX_RDY,
			ACK_out   	=>	Ack_out,--ports are connected to the signals and then to each other through the signals
			Valid_D   	=>	Valid_D,
			TX_Data   	=>	TX_Data,
			CS        	=>	CS,
			Write_en   	=>	Write_en,--signal connected to ram n dma
			OE        	=>	OE ,
			Address   	=>	Address,
			Databus   	=>	Databus,
			DMA_ACK   	=>	DMA_ACK,
			Send_comm 	=>	Send_comm,
			DMA_RQ    	=>	DMA_RQ,
			READY      	=>	READY);
----------------------------------------------------------------------------------------




end behavior;

